A critical component of growing any ecosystem is to have enablement available for respective developers. This includes specifications, tools, and reference designs. Below is a list of available enablement today. It is suggested to periodically visit as more enablement will be added over time.

OMI ARCHITECTURE SPECIFICATIONS

Design Overview
A general understanding of OMI is helpful before consuming architecture and design details. The following OMI reference material (PDF) shows block diagrams of the OMI stack, PCIe interoperability, and the relationship of OMI to the Data Link layer and Transaction Link layer.

The OMI architecture specification is a subset of the OpenCAPI bus and includes:

  • OpenCAPI Transaction Link (TL) Architecture Specification 3.1
  • OpenCAPI Data Link (DL) Architecture Specification.

The TL Architecture Specification 3.1 is highly tuned based on decades of experience in making a ‘clean sheet architecture’ by making tradeoff decisions to focus the architecture for a direct link to memory. The specifications can be downloaded here OpenCAPI Consortium: Official Site.

32Gbps PHY SIGNALING SPECIFICATION

The OMI bus protocol will be running over a 32Gbps PHY.  Equally important to the OMI bus is the Data Link Layer to be interfacing with this PHY.

  • OpenCAPI 32Gbps PHY Signaling Specification

This PHY Signaling Specification will provide you further guidance in how the TL will interface to the DL and PHY.  The specifications can be downloaded here OpenCAPI Consortium: Official Site.

OMI FPGA REFERENCE DESIGN (FIRE) AND BOARD IMPLEMENTATION (APOLLO) OF THE HOST PROCESSOR SIDE

Fire is a FPGA reference design in RTL that represents OMI on the host side. A physical implementation of Fire onto a reference board design is called Apollo (coming soon). Fire can drive five x8 OpenCAPI links, which drive four DDIMM sockets and one OCMB socket, generating traffic similar to real functional traffic and checking the results. This reference design is architected with a single universal address map and also contains miscellaneous facilities for various forms of debug, such as ways to send custom OpenCAPI commands and numerous ways to send MMIO commands. Since these reference designs are open source, you can tailor them to meet your needs (e.g., add new functions for investigating or learning).

OMI FPGA REFERENCE DESIGN (ICE) AND BOARD IMPLEMENTATION (GEMINI) OF THE DEVICE SIDE

Ice is a FPGA reference design in RTL that represents OMI on the device side. Additional information on Ice can be found in the ICE Workbook,  A physical implementation of Ice onto a reference board design is called Gemini (coming soon). Ice includes the OpenCAPI 3.1 TLx reference design as well as components such as the AFU main data flow logic, asynchronous crossing domain and memory controller user interface. On the ICE top, Xilinx GTY transceiver communicates to a processor host through x8 OpenCAPI lanes and Xilinx DDR4 Memory Interface IPs connected to the 32GB of DDR4 memory. The entire Ice RTL is built on the Xilinx Zynq UltraScale+ FPGA ZU19EG-2FFVC1760I. Since these reference designs are open source, you can tailor them to meet your needs (e.g., add new functions for investigating or learning).

OMI MEMORY CONTROLLER REFERENCE DESIGN

This FPGA reference design in RTL is a subset of ICE design and is predominantly a memory controller. This OMI being on the device side is open source and allows flexibility for the implementer and can be found at the following:
https://github.com/OpenCAPI/omi_device_ice/blob/master/vhdl/ice_mc_top.vhdl

OMI ASIC DEVICE REFERENCE DESIGN

This repository contains the RTL to leverage OMI technology for an ASIC memory buffer or related device.  What’s included:

  • TLx (Transaction Layer)
  • DLx (Data Link Layer)

The macros conform to the TL and DL 3.1 Architecture specifications.  These specifications can be downloaded from http://www.opencapi.org.

The GitHub link to access the design is https://github.com/OpenCAPI/omi_asic_device_reference_design