One OMI initiative underway is to have a forum where projects are available for developers, researchers, and educational institutions to join forces in creating industry memory solutions involving OMI.  The forum will be one that is open where IP can freely flow between contributors and other participants and adopters with interest to apply the results as they wish.  Below are projects that have completed and proposals for those that are yet to launch.  Any questions or comments, please reach out to the OpenCAPI Technical Director (OCCTechDir@opencapi.org) today!

Product Developers and Data Center Developers welcomed! Have any ideas to submit or interested in joining? Contact the OCC Technical Director today!

COMPLETED PROJECTS

Fire and Apollo – OMI FPGA Reference Design and Implementation of the host processor side

Fire is a FPGA reference design in RTL that represents OMI on the host side. A physical implementation of Fire onto a reference board design is called Apollo (coming soon). Since these reference designs are open source, you can tailor them to meet your needs (e.g., add new functions for investigating or learning).

Ice and Gemini – OMI FPGA Reference Design and Implementation of the device side

Ice is a FPGA reference design in RTL that represents OMI on the device side. Additional information on Ice can be found in the ICE Workbook,   A physical implementation of Ice onto a reference board design is called Gemini (link coming soon). Ice includes the OpenCAPI 3.1 TLx reference design as well as components such as the AFU main data flow logic, asynchronous crossing domain and memory controller user interface. The entire Ice RTL is built on the Xilinx Zynq UltraScale+ FPGA ZU19EG-2FFVC1760I. Since these reference designs are open source, you can tailor them to meet your needs (e.g., add new functions for investigating or learning).

IDEAS FOR FUTURE OMI PROJECTS

ASIC Chiplet Interconnect

Proposal would be to create a chiplet interconnect bus to be used on an ASIC. OMI technology would be utilized for optimal performance in the design of a memory solution or for a SOC solution that leverages a significant size of Near Memory in a chiplet construct.

Dual OMI E3.S Memory Module

Proposal would be to create a dual OMI E3.S Memory Module. The first deliverable would be similar to the Samsung’s CXL.mem FPGA E3.S module. The second deliverable would be based on Microchip’s memory buffer chip.

OCP Compliant Memory Pooling System Proof-of-Concept

Proposal would be to create a Proof-of-Concept (POC) OMI DDIMM memory pool system based around the concepts in development within the OCP HPC Sub-project. First delivery would be an opensource reference design and hardware build, including POWER10 and FPGA modules with OMI DDIMMS, that can be plugged into an OCP OAI chassis. The second delivery would be a demonstration of an application at a premier conference(s).

OMI enabled High Bandwidth Memory (HBM)

Proposal would be to create HBM capable of interfacing to a host on an OMI bus.

Seamless Transition Enablement of DDR DIMM to OMI DDIMM

Proposal would be to create a FPGA RTL shim that would enable DDR DIMMs to be interchangeable with OMI DDIMMs. The shim will be compatible with the standard FPGA External Memory Interface (EMI) and will attach to the FPGA OMI Memory Controller. Consequently, this also will allow higher level tools like HLS and VITIS to seamlessly support OMI DDIMMs.