About the Open Memory Interface (OMI)

WHY OMI

The growth of data processed and stored, and the new ways that computers are being used, are causing memory capacity and performance requirements to balloon. Near Memory, the memory connected directly to a processor’s pins, must grow larger and faster to keep pace. However, industry’s response with the DDR bus and High Bandwidth Memory (HBM) failed to meet the needs of Near Memory while the newly introduced bus standards (CAPI in 2014, OpenCAPI, CCIX, and Gen-Z in 2016, and CXL in 2019) only solved memory size with slower access to Far Memory. None of these satisfy the need for larger Near Memories with high bandwidths and low latencies other than OMI.

Specification	LRDIMM DDR4	DDR5	HBM2E(8-High)	OMI
Protocol	Parallel	Parallel	Parallel	Serial
Signalling	Single-Ended	Single-Ended	Single-Ended	Differential
I/O Type	Duplex	Duplex	Simplex	Simplex
Paths/Channel (Read/Write)	64	32	512R/512W	8R/8W
Data Transfer Rate	3,200MT/s	6,400MT/s	3,200MT/s	32,000MT/s
Channel Bandwidth (R+W)	25.6Gbytes/s	25.6Gbytes/s	400Gbytes/s	64Gbytes/s
Latency	41.5ns		60.4ns	45.5ns
Channels / Processor Die	8 (EPYC Rome IO)		5 (NVidia Ampere)	16 (POWER10)
Processor Die Size	416mm²		826mm²	602mm²
Driver Area / Channel	7.8mm²	3.9mm²	11.4mm²	2.2mm²
Bandwidth / mm²	3.3GBytes/s/mm²	6.6GBytes/s/mm²	35GBytes/s/mm²	29.6GBytes/s/mm²
Max Capacity / Channel	64GB	256GB	16GB	256GB
Connection	Multi Drop	Multi Drop	Point-to-Point	Point-to-Point
Data Resilience	Parity	Parity	Parity	CRC

If you have questions or want more details on this graph, contact the OCC Technical Director.

OMI is a highly tuned bus that was developed for near memory and is easily migratable to emerging memory solutions (e.g., Storage Class Memory). This serial coherent bus, a subset of OpenCAPI, was architected specifically for the interface between a processor and Near Memory having absolute minimum latency with significant bandwidth and capacity. OMI is the solution to our evolving industry’s demand for Near Memory as data centers evolve from compute centric to becoming data centric.