About the Open Memory Interface (OMI)Tom DuHamel2022-02-04T16:40:14+00:00
The growth of data processed and stored, and the new ways that computers are being used, are causing memory capacity and performance requirements to balloon. Near Memory, the memory connected directly to a processor’s pins, must grow larger and faster to keep pace. However, industry’s response with the DDR bus and High Bandwidth Memory (HBM) failed to meet the needs of Near Memory while the newly introduced bus standards (CAPI in 2014, OpenCAPI, CCIX, and Gen-Z in 2016, and CXL in 2019) only solved memory size with slower access to Far Memory. None of these satisfy the need for larger Near Memories with high bandwidths and low latencies other than OMI.
OMI is a highly tuned bus that was developed for near memory and is easily migratable to emerging memory solutions (e.g., Storage Class Memory). This serial coherent bus, a subset of OpenCAPI, was architected specifically for the interface between a processor and Near Memory having absolute minimum latency with significant bandwidth and capacity. OMI is the solution to our evolving industry’s demand for Near Memory as data centers evolve from compute centric to becoming data centric.
What the Analysts have to say about OMI
“The Future of Low-Latency Memory, Why Near Memory Requires a New Interface“