The growth of data processed and stored, and the new ways that computers are being used, are causing memory capacity and performance requirements to balloon. Near Memory, the memory connected directly to a processor’s pins, must grow larger and faster to keep pace. However, industry’s response with the DDR bus and High Bandwidth Memory (HBM) failed to meet the needs of Near Memory while the newly introduced bus standards (CAPI in 2014, OpenCAPI, CCIX, and Gen-Z in 2016, and CXL in 2019) only solved memory size with slower access to Far Memory. None of these satisfy the need for larger Near Memories with high bandwidths and low latencies other than OMI.